1. Field of the Invention
The present invention relates to power semiconductor devices used as components for controlling power supplies in mobile devices such as mobile phones and digital still cameras, in peripheral devices of personal computers (e.g., liquid-crystal or CRT displays, printers, video tape recorders and DVD players), or in electronic devices mounted on vehicles, and relates more particularly to a power semiconductor device which has MOS-structure semiconductor elements (such as vertical power MOSFETs or IGBTs) with relatively-low withstand voltage (of e.g., less than 200 V) and at least one Zener diode, or input protection circuit, provided between a gate of the MOS-structure semiconductor elements and one main electrode thereof (a source of the vertical power MOSFETs or a cathode of the IGBTs).
2. Description of the Background Art
Conventionally, power-supply voltages of 10 V, 4 V or 2.5 V have been used to drive the power semiconductor devices for controlling the power supply. In the recent markets, however, particularly in the field of mobile devices such as mobile phones, the demand for lower-voltage-driven power semiconductor devices which are driven at 2.5 V or 1.5 V is escalating for the requirement of controlling charge and discharge of lithium-ion battery with lower consumption power. The markets are also intensively demanding, as well as the driving voltage reduction, improvements in device performance of the power semiconductor devices, such as on-state voltage reduction through reduction in on-state resistance of the MOS-structure semiconductor elements, and capacity reduction through further reduction in chip size. Moreover, the market and law regulations are even demanding that the power semiconductor devices should be equipped with input protection circuits for protecting gate insulating films of the MOS-structure semiconductor elements from various noises, such as static electricity produced from human body during handling of the devices or that produced from machines, lightning, electromagnetic waves and inrush currents produced during operation of car starters. For measures against such noises as static electricity, the power semiconductor devices are required to satisfy, for example, the EIAJ standards (Electronic Industries Association of Japan). That is to say, the HBM (Human Body Method) requires the products to meet the withstand voltage standard of 1000 V, and the MN (Machine Method) requires withstand voltage of 100 V or higher. As the markets are demanding products having higher withstand voltage characteristics, it is an urgent need to realize power semiconductor devices having withstand voltage characteristics superior to those required by the EIAJ standards.
To satisfy such demands from customers, recent power-supply-controlling power semiconductor devices are even equipped with Zener diodes as the input protection circuits for protecting the MOS-structure semiconductor elements. For example, as the market for mobile phones grows, chips having an area of 2 mm2 and input capacity which corresponds to 1000 pF have been appearing on the market as Zener-diode-containing vertical power MOSFET devices. In the field of mobile phones where the products have withstand voltages of 20 to 30 V, particularly, there is an intensive demand for products with lower withstand voltage and lower on-state resistance.
FIG. 20 is a plan view showing a Zener diode forming an input protection circuit for trench-type n-type MOSFETs, where the shape of a gate electrode 6PP is depicted schematically rather than exactly. FIG. 21 is the vertical section taken along the line AP-BP in FIG. 20. For convenience of description, FIG. 20 does not show a passivation film 10PP shown in FIG. 21.
In FIGS. 20 and 21, a semiconductor substrate 100PP is composed of an N+ substrate 9PP and an Nxe2x88x92 epitaxial layer 8PP; a surface of the Nxe2x88x92 epitaxial layer 8PP, which forms a main surface of the semiconductor substrate 100PP, is covered by an insulating film 7PP, and an N+ type layer 1PP1 is formed on a surface 7SPP of the insulating film 7PP. A P type layer 31PP is formed along the periphery of the N+ type layer 1PP1 and thus entirely surrounds it, an N+ type layer 32PP is formed along the periphery of the P type layer 31PP and thus entirely surrounds it, and a P type layer 33PP is formed along the periphery of the N+ type layer 32PP and thus entirely surrounds it; the layers 31PP, 32PP and 33PP form a PN junction region 3PP. Further, an N+ type layer 1PP2, the outermost layer, is formed along the periphery of the PN junction region 3PP and thus entirely surrounds it. In this way, the semiconductor regions are formed so that the N+ type layer 1PP1 in the center is surrounded by the P type and N type layers in series, thereby forming a Zener diode 11PP having an N+-P-N+-P-N+ structure. The passivation film 10PP is formed on the surface of the Zener diode 11PP; the passivation film 10PP has a gate-side contact region 4PP formed over the N+ type layer 1PP1 and a source-side contact region 2PP formed over the N+ type layer 1PP2. A gate electrode 6PP is formed in the gate-side contact region 4PP, and a source electrode 5PP is formed in a surface of the passivation film 10PP around a gate pad formation region and fills the source-side contact region 2PP. A drain electrode 12PP is formed on a back surface of the N+ substrate 9PP.
As described above, in the conventional Zener-diode-containing vertical power MOSFET device, the Zener diode 11PP having N+-P-N+-P-N+ structure is provided right under the gate pad and its vicinity in the main surface of the semiconductor substrate 100PP.
When applying wire-bonding to the gate electrode in the gate pad so as to package the IC, gold (Au) wire having a diameter of 50 xcexcm is usually used. For this process, a square gate pad must be sized to offer an area which corresponds to 200 xcexcmxc3x97200 xcexcm at least.
Suppose that a Zener diode is formed as shown in FIGS. 20 and 21 right under a gate pad having an area which corresponds to 200 xcexcmxc3x97200 xcexcm and in its vicinity in a vertical power MOSFET device (the peripheral length of the gate pad is 0.8 mm). When the electrostatic strength of this vertical power MOSFET device is measured by using an electrostatic strength testing circuit for HBM as shown in FIG. 22, it shows the current-voltage (I-V) characteristic as shown by the broken line in FIG. 6. That is to say, since the withstand voltage value of the Zener diode increases in proportion to the current, the voltage value may exceed the breakdown voltage limit of the gate insulating film, depending on the current value. Accordingly, in this case, the provision of the Zener diode offers no effect at all. Furthermore, as shown in FIG. 23 (FIG. 23 shows data which has not been disclosed before and it plots the lowest values of the measurements), the operating resistance, or the series resistance, of the Zener diode in this case is about 100 xcexa9, in which case the electrostatic strength (HBM(+)) is even lower than 1000 V, which is far from satisfying the desired standard value (=1500 V) which the inventor of this invention expects. It is thus understood that disposing a Zener diode right under, and in the vicinity of, the gate pad having a peripheral length of 0.8 mm provides no effect.
Accordingly, the inventor of this invention carried out attempts to increase the area or the peripheral length of the gate pad, i.e., to increase the area of a Zener diode formation region right under the gate pad. FIG. 24 shows the tested results (data which has not been disclosed before). As shown in FIG. 24, as the gate pad area or the PN junction width of the Zener diode increases (the PN junction width is the length along the periphery of a PN junction face), the current-voltage (I-V) characteristic curve shifts to the left in FIG. 24, i.e., the curve becomes steeper. This shows that the operating resistance decreases and the Zener diode effect is enhanced. Analyzing this phenomenon on the basis of FIGS. 23 and 25 (not disclosed before) and FIG. 26 (FIG. 26 shows data which has not been disclosed before and it plots mean values of the measurements) shows the following. That is to say, when the data is evaluated at the lowest values of measurements, the withstand voltage can be 1000 V at the operating resistance of 30 xcexa9 (HBM(+) is the withstand voltage value upon application of a positive bias and HBM(xe2x88x92) is that upon application of a negative bias), in which case the PN junction width is 1.6 mm. In other words, when the peripheral length of the gate pad is set to 1.6 mm, or when the length of one side of the gate pad is 400 xcexcm, twice that of the conventional one, the mean withstand voltage is 4000 V or higher, which sufficiently satisfies the above-stated desired standard value (=1500 V).
It is thus understood that a Zener-diode-containing vertical power MOSFET device which satisfies the withstand voltage standard can be realized by forming the gate pad having an area which corresponds to 400 xcexcmxc3x97400 xcexcm. When such a large-area gate pad is used and a built-in Zener diode is formed right under the gate pad, however, the rate of occupied area of the gate pad in the whole device reaches as much as 18% and that of the unit cell portion is necessarily reduced. This problem becomes more serious as the chip is smaller-sized. In this respect, in the above-described conventional product having the gate pad area of 200 xcexcmxc3x97200 xcexcm, the rate of occupied area of the gate pad is no more than 2% and therefore the above problem hardly rises even when the chip is smaller-sized.
Thus, considering that wire-bonding using 50-xcexcm gold (Au) wire essentially requires a gate pad having an area which corresponds to 200 xcexcmxc3x97200 xcexcm, and that such a gate pad as has this area does not cause the above-described problem even when the chip size is reduced, a Zener-diode-containing power semiconductor device is being demanded which adopts a gate pad whose one side is 200 xcexcm long, to achieve size reduction and allow increased effective area for the unit cell portion, and which can achieve reduced operating resistance of the Zener diode, and hence a withstand voltage equal to or higher than the above-stated desired standard value (=1500 V), so as to prevent deterioration of the characteristics of the gate insulating film.
The present invention is directed to a power semiconductor device. According to a first aspect of the present invention, the power semiconductor device comprises: a semiconductor substrate; a unit cell portion comprising a plurality of MOS-structure power semiconductor elements formed on a first region which occupies the central part of a main surface of the semiconductor substrate, the unit cell portion comprising a recessed part; a gate pad portion comprising a wire-bonding-target gate electrode formed over a second region surrounded by the recessed part of the unit cell portion in the main surface of the semiconductor substrate; and a chip periphery portion comprising at least one Zener diode formed over a third region entirely surrounding the periphery of the unit cell portion in the main surface of the semiconductor substrate.
According to a second aspect of the present invention, in the power semiconductor device of the first aspect, the chip periphery portion comprises one Zener diode, and the Zener diode comprises n semiconductor regions arranged one outside another from the first region located on the side of the periphery of the unit cell portion to the n-th region located on the side of the periphery of the semiconductor substrate, the n semiconductor regions having alternating conductivity types and forming junctions one surrounding another along the periphery of the semiconductor substrate, the n being an odd number of three or larger.
According to a third aspect of the present invention, in the power semiconductor device of the first aspect, the chip periphery portion comprises a plurality of first Zener diodes, and a plurality of second Zener diodes, and in the power semiconductor device of the third aspect, each of the plurality of first Zener diodes comprises n semiconductor regions arranged one outside another from the first semiconductor region having a first conductivity type and located in the center, the n semiconductor regions having alternating conductivity types and forming junctions one surrounding another, the n being an odd number of three or larger, the n-th semiconductor region in each of the plurality of first Zener diodes having the first conductivity type, the first semiconductor region in each of the plurality of first Zener diodes being electrically connected, through a first contact hole formed on a surface of the first semiconductor region, to the wire-bonding-target gate electrode in the gate pad portion and to a first gate electrode layer of a corresponding first MOS-structure power semiconductor element provided in the unit cell portion, the n-th semiconductor region which is the outermost one in each of the plurality of first Zener diodes being electrically connected, through a second contact hole formed on a surface of the n-th semiconductor region, to one main electrode layer of the first MOS-structure power semiconductor element in the unit cell portion, and in the power semiconductor device of the third aspect, each of the plurality of second Zener diodes comprises n semiconductor regions arranged one outside another from the first semiconductor region having the first conductivity type and located in the center, the n semiconductor regions having alternating conductivity types and forming junctions one surrounding another, the n being an odd number of three or larger, the n-th semiconductor region in each of the plurality of second Zener diodes having the first conductivity type, the n-th semiconductor region which is the outermost one in each of the plurality of second Zener diodes being electrically connected, through a third contact hole formed on a surface of the n-th semiconductor region, to the wire-bonding-target gate electrode in the gate pad portion and to a second gate electrode layer of a corresponding second MOS-structure power semiconductor element in the unit cell portion, the first semiconductor region in each of the plurality of second Zener diodes being electrically connected, through a fourth contact hole formed on a surface of the first semiconductor region, to one main electrode layer of the second MOS-structure power semiconductor element in the unit cell portion, the first gate electrode layer and the second gate electrode layer being electrically connected to each other.
According to a fourth aspect of the present invention, in the power semiconductor device of the third aspect, a first sum total of first areas of the first contact holes of the plurality of first Zener diodes and third areas of the third contact holes of the plurality of second Zener diodes is equal to a second sum total of second areas of the second contact holes of the plurality of first Zener diodes and fourth areas of the fourth contact holes of the plurality of second Zener diodes.
According to a fifth aspect of the present invention, in the power semiconductor device of the fourth aspect, the plurality of first Zener diodes and the plurality of second Zener diodes are alternately arranged along the periphery of the semiconductor substrate.
According to a sixth aspect of the present invention, in the power semiconductor device of the fifth aspect, a common gate electrode layer is formed between adjacent ones of the first Zener diodes and the second Zener diodes in the chip periphery portion, the common gate electrode layer being connected to both of the first gate electrode layer and the second gate electrode layer, and the first semiconductor region of the first Zener diode and the n-th semiconductor region of the second Zener diode are electrically connected to each other through a fifth contact hole formed on a surface of the common gate electrode layer and a gate electrode interconnection filling the fifth contact hole.
In the power semiconductor device of the first aspect of the present invention, since the Zener diode is provided in the chip periphery portion, the rate of occupied area of the gate pad portion in the semiconductor device can be remarkably reduced and as a result, it becomes possible to easily realize enlargement of the effective cell region of each semiconductor element in the unit cell portion and ensure reduction of on-state resistance and on-state voltage.
In the power semiconductor device of the second aspect of the present invention, it is possible to remarkably increase the PN junction width of one Zener diode and achieve a significant improvement in current-voltage characteristic of the Zener diode through remarkably reduction in operating resistance of the Zener diode. The present invention can thus provide a power semiconductor device having a greatly enhanced function of protecting the gate insulating film from noises such as static electricity.
In the power semiconductor device of the third aspect of the present invention, since further increase in PN junction width (further reduction in operating resistance) can be achieved as compared with that in the second aspect, it is possible to realize more significant improvement in current-voltage characteristic and further enhancement in protection function against noises such as static electricity. The third aspect also produces an effect of enabling easy and flexible control of the amount of increase in PN junction width or the amount of reduction in operating resistance.
In the power semiconductor device of the fourth aspect of the present invention, it is possible to obtain symmetric bidirectionality in the current-voltage characteristics of the Zener diodes, while further enhancing the Zener diode effect (input protection function).
In the power semiconductor device of the fifth aspect of the present invention, the Zener diode effect (input protection function) can be further enhanced easily and certainly, and the symmetrical bidirectionality of the current-voltage characteristics of the Zener diodes can be achieved easily and certainly.
In the power semiconductor device of the sixth aspect of the present invention, the gate electrode interconnection is facilitated and the Zener diode effect can be further enhanced by utilizing the proximate interconnection structure.
The present invention has been made to meet the above-described technical demands, thereby realizing a power semiconductor device which can achieve the objects below.
(1) A first object of the present invention is to downsize the gate pad portion (the target rate of its occupied area is about 2%) for ensuring enlargement of the effective area for the cell operation region (also referred to as cell active region) in the unit cell portion of a small-size small-capacity chip, leading to reduction in on-state resistance or on-state voltage.
(2) A second object of the present invention is to ensure enhancement in electrostatic strength through reduction in operating resistance by improvement in I-V characteristic of the Zener diodes, and to thereby achieve products highly resistant to noises such as static electricity.
(3) A third object of the present invention is to make it possible to freely adjust and control the operating resistance of the Zener diodes.
(4) A fourth object of the present invention is to achieve symmetrical bidirectionality in the I-V characteristic of the Zener diodes.
(5) A fifth object of the present invention is to realize easier and shorter gate electrode interconnection for further enhancement in input protection effect of the Zener diodes.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.